This invention relates to the field of binary logic circuit design, and more particularly to methods of designing logic circuits for implementation in CMOS integrated circuit devices, or the like, that maximize circuit density while minimizing circuit delay.
Every designer and manufacturer of integrated circuits currently faces two formidable obstacles to performance improvements. First, further increases in circuit density require design and implementation of sub-micron feature size devices This effort requires vast investments of resources in new equipment and techniques. Second, even assuming success in building sub-micron devices, operation of circuits with transistor gate lengths substantially smaller than one micron is limited by breakdown voltages less than the five volt supply voltage level now standard for virtually all logic devices throughout the industry. Lower supply voltages compromise noise immunity and are incompatible with existing components and systems. Substantial investment in research, development and implementation of new processes and materials is being made in an attempt to overcome these limitations.
Such changes are likely to come about relatively slowly. In the interim, improved performance must be achieved by improved designs using existing technologies. Improvements in performance of some kinds of logic circuits have been achieved through the use of pass transistors or transmission gate structures. However, design of logic circuits using such technologies, particularly design of higher order logic functions (for example, functions of greater than three variables) remains a challenge. Optimizing such circuits to maximize density and performance has been achieved largely through trial and error and intuition developed by those skilled in the art. This kind of subjective circuit design approach, however, is very limiting and cannot be automated for computer-assisted design.
U.S. Pat. No. 4,710,649 (Lewis) discloses transmission gate logic circuits for implementing fundamental boolean combinations such as AND and OR functions. The '649 patent shows simplified or reduced versions of two and three input AND and OR gates for reducing transistor count, and suggests cascading additional stages to form a circuitry for implementing higher order functions. (See the discussion of FIG. 3, below.) However, there is no disclosure of a systematic way to simplify or reduce transmission gate logic circuits generally. The '649 patent makes no suggestion of how to approach design of a high order boolean function using transmission gate logic circuits.
U.S. Pat. No. 4,566,064 (Whitaker) presents a design methodology for constructing circuits using pass transistors to implement logic functions. The method disclosed in the '064 patent, however, has several drawbacks. First, in circuits designed in accordance with the '064 method, a substantial propagation delay results from connecting more than two transmission gate outputs in parallel. This results in larger output parasitic capacitants, a major contributor to delay in CMOS designs.
Second, the '064 patent does not suggest how to reduce a resulting design. Therefore, for a large number of inputs, the number of required circuit elements, such as transmission gates, increases geometrically with the number of input variables. Finally, the method described in the '064 patent is difficult to simulate on existing gate-level simulation programs because two or more transmission gate output terminals can be ON in parallel, thus requiring the simulator software to resolve this apparent driver conflict by applying varied signal strengths.
A basic primer on CMOS transmission gates and their use is E. Hnatek, USER'S GUIDEBOOK TO DIGITAL CMOS INTEGRATED CIRCUITS (McGraw-Hill 1981) pp. 34-41. A combinational multiplier circuit that includes the use of transmission gates in an adder cell is shown in R.R. Shively, et al. "Cascading Transmission Gates to Enhance Multiplier Performance" IEEE Transactions on Computers, Vol. c-33, No. 7, Jul. 1984. Pass transistor logic is used in "A 3.8 ns 16.times.16 Multiplier Using Complementary Pass Transistor Logic," by K. Yano, et al, IEEE 1989 Custom Integrated Circuits Conference. None of these references suggests a systematic method for design of digital circuits using transmission gate logic.
The problem of digital signal propagation delay through a string of pass transistors is recognized, and a solution suggested, in U.S. Pat. No. 4,536,855 (Morton). An MOS binary multiplication cell circuit with reduced transistor count is shown in U.S. Pat. No. 4,363,107 (Ohhashi et al.). Ohhashi et al., however, does not disclose a method of designing circuits of the type shown.
Other references of interest are Carver Mead and Lynn Conway, "Introduction to VLSI Systems," Addison Wesley Publishing, Chapters 1, 3, 5 and 9, 1980, and Neil Wesle and Kamran Eshraghian, "Principles of CMOS VLSI Design," Addison Wesley Publishing, Chapters 2 and 5, 1985.
Accordingly, the need remains for a better method of designing and constructing logic circuits to gain improvements in speed and performance over the state of the art.
The object of the invention is to systematize the design and optimization of boolean logic circuitry implemented with transmission gate circuit elements.